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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com october 2004 rev. 7 w3eg7266s-ad4 -bd4 preliminary* white electronic designs 512mb C 64mx72 ddr sdram unbuffered ecc w/pll features double-data-rate architecture ddr200, ddr266, ddr300 and ddr400 ? jedec design speci? cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect power supply: ? v cc = v ccq = +2.5v 0.2v (100, 133 and 166mhz) ? v cc = v ccq = +2.6v 0.1v (200mhz) jedec standard 200 pin so-dimm package ? package height options: ad4: 35.05 mm (1.38) bd4: 31.75 mm (1.25) note: consult factory for availability of: ? lead-free products ? vendor source control options ? industrial temperature options description the w3eg7266s is a 64mx72 double data rate sdram memory module based on 512mb ddr sdram components. the module consists of nine 64mx8 ddr sdrams in 66 pin tsop packages mounted on a 200 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * this data sheet describes a product that is not fully quali? ed or characterized and is subject to change without notice. operating frequencies ddr400@cl=3 ddr333@cl=2.5 ddr266@cl=2 ddr266@cl=2.5 ddr200@cl=2 clock speed 200mhz 166mhz 133mhz 133mhz 100mhz cl-t rcd -t rp 3-3-3 2.5-3-3 2-2-2 2.5-3-3 2-2-2
w3eg7266s-ad4 -bd4 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary pin names pin configuration a0 C a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobe input/output ck0 clock input ck0# clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-dqm8 data-in mask v cc power supply v ss ground v ref power supply for reference v ccspd serial eeprom power supply sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc identi? cation flag nc no connect pin symbol pin symbol pin symbol pin symbol 1vref51 v ss 101 a9 151 dq42 2vref52 v ss 102 ab 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dqo 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7 dq1 57 v cc 107 a5 157 v cc 8dq558v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqso 61 dqs3 111 al 161 v ss 12 dqmo 62 dqm3 112 ao 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10/ap 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 rao 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dqm6 21 v cc 71 cbo 121 cso 171 dq50 22 v cc 72 cb4 122 nc 172 dq54 23 dq9 73 cb1 123 nc 173 v ss 24 dq13 74 cb5 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dqm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dqs8 127 dq32 177 dq56 28 v ss 78 dqm8 128 dq36 178 dq60 29 dq10 79 cb2 129 dq33 179 v cc 30 dq14 80 cb6 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 cb3 133 dqs4 183 dqs7 34 v cc 84 cb7 134 dqm4 184 dqm7 35 cko 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 cko# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sao 45 v cc 95 nc 145 dq41 195 scl 46 v cc 96 ckeo 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dqm2 98 nc 148 dqm5 198 sa2 49 dq18 99 a12 149 v ss 199 v ccid 50 dq22 100 a l l 150 v ss 200 nc
w3eg7266s-ad4 -bd4 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary functional block diagram ba0, ba1 a0-a12 ras# cas# cke0 we# ba0, ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams we#: ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 s0# dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm4 dqs4 dm1 dqs1 dm5 dqs5 dm2 dqs2 dm6 dqs6 dm cs# dqs dm cs# dqs dm cs# dq dm cs# dq dm cs# dqs dm3 dqs3 dm7 dqs7 dm8 dqs8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v ccspd v cc v ref v ss spd/eeprom ddr sdrams ddr sdrams ddr sdrams dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq a0 sa0 serial pd sda a1 sa1 a2 sa2 wp scl ck0a# ck0 ck0a pll freq_sel v cc ck0# ddr sdram 120 ck0 ck0# 120 ddr sdram ck1 ck1# ddr sdram 120 ck2 ck2# ddr sdram 120 note: all resistor values are 22 ohms unless otherwise speci? ed
w3eg7266s-ad4 -bd4 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out C 0.5 ~ 3.6 v voltage on v cc supply relative to v ss v cc , v ccq C1.0 ~ 3.6 v storage temperature t stg C 55 ~ +150 c power dissipation p d 9w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70 c, v cc = 2.5v 0.2v parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref 1.15 1.35 v termination voltage v tt 1.15 1.35 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il C 0.3 v ref C 0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt C 0.76 v capacitance t a = 25c, f = 1mhz, v cc = 2.5v 0.2v parameter symbol max unit input capacitance (a0-a12) c in1 29 pf input capacitance (ras#,cas#,we#) c in2 29 pf input capacitance (cke0,cke1) c in3 29 pf input capacitance (ck0,ck0#) c in4 5.5 pf input capacitance (cs0#,cs1#) c in5 29 pf input capacitance (dqm0-dqm8) c in6 8pf input capacitance (ba0-ba1) c in7 29 pf data input/output capacitance (dq0-dq63)(dqs) c out 8pf data input/output capacitance (cb0-cb7) c out 8pf
w3eg7266s-ad4 -bd4 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary i dd specifications and test conditions 0c t a 70c, v cc = v ccq = 2.5v 0.2v (100, 133, 166mhz), v cc = v ccq = +2.6v 0.1v (200mhz) parameter symbol conditions ddr400@ cl=3 ddr333@ cl=2.5 ddr266@ cl=2, 2.5 ddr200@ cl=2 units max max max max operating current i dd0 one device bank; active - precharge; (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. t rc =t rc (min); t ck =t ck 1670 1445 1445 1445 ma operating current i dd1 one device bank; active- read-precharge; burst = 2; t rc =t rc (min);t ck =t ck (min); iout = 0ma; address and control inputs changing once per clock cycle. 1940 1715 1715 1715 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck =t ck (min); cke=(low) 45 45 45 45 ma idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 770 680 680 680 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke=(low) 405 315 315 315 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 815 725 725 725 ma operating current i dd4r burst = 2; reads; continous burst; one device bank active;address andcontrol inputs changing once per clock cycle; t ck =t ck (min); i out = 0ma. 1985 1760 1760 1760 ma operating current i dd4w burst = 2; writes; continous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing twice per clock cycle. 2030 1850 1670 1670 ma auto refresh current i dd5 t rc =t rc (min) 3360 2885 2885 2885 ma self refresh current i dd6 cke 0.2v 320 320 320 320 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands 4325 3875 3875 3875 ma
w3eg7266s-ad4 -bd4 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary i dd1 : operating current : one bank 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck= 10ns, cl2, bl=4, t rcd= 2*t ck , t ras= 5*t ck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck= 7.5ns, cl=2.5, bl=4, t rcd= 3*t ck , t rc= 9*t ck , t ras= 5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl=2, bl=4, t rcd =3*t ck , t rc =9*t ck , t ras =5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rcd =10*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr400 (200mhz, cl=3) : t ck =5ns, bl=4, t rcd =15*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current : four banks 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. iout=0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck =10ns, cl2, bl=4, t rrd =2*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck =7.5ns, cl=2.5, bl=4, t rrd =3*t ck , t rcd =3*t ck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl2=2, bl=4, t rrd =2*t ck , t rcd =2*t ck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rrd =3*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr400 (200mhz, cl=3) : t ck =5ns, bl=4, t rrd =10*t ck , t rcd =15*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend : a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
w3eg7266s-ad4 -bd4 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions ddr400: v cc = v ccq = +2.6v 0.1v ac characteristics 403 335 262 265 202 parameter symbol min max min max min max min max min max units notes access window of dqs from ck/ck# t ac -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 0.75 -0.8 0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 25 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 25 clock cycle time cl = 3 t ck (3) 5 7.5 6 13 7.5 13 7.5 13 8 13 ns 38, 43 cl = 2.5 t ck (2.5) 6 13 7.5 13 7.5 13 7.5/10 13 10 13 ns 38, 43 cl = 2 t ck (2) 7.5 13 ns 37, 42 dq and dm input hold time relative to dqs t dh 0.4 0.45 0.5 0.6 ns 22, 26 dq and dm input setup time relative to dqs t ds 0.4 0.45 0.5 0.6 ns 22, 26 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 2 ns 26 access window of dqs from ck/ck# t dqsck -0.6 +0.6 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 0.45 0.5 0.5 0.6 ns 22 write command to ? rst dqs latching transition t dqss 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl t ch, t cl t ch, t cl ns 29 data-out high-impedance window from ck/ck# t hz +0.70 +0.70 +0.75 +0.75 +0.8 ns 16, 35 data-out low-impedance window from ck/ck# t lz -0.70 -0.70 -0.75 -0.75 -0.8 ns 16, 35 address and control input hold time (1 v/ns) t ihf 0.6 0.75 0.90 0.90 1.1 ns 12 ns 12 address and control input setup time (1 v/ns) t isf 0.6 0.75 0.90 0.90 1.1 ns 12 address and control input hold time (0.5 v/ns) t ihs 0.6 0.80 1 1 1.1 ns 12 address and control input setup time (0.5 v/ns) t iss 0.6 0.80 1 1 1.1 ns 12 address and control input pulse width (for each input) t ipw 2.20 2.2 2.2 2.2 2.2 ns load mode register command cycle time t mrd 2 12151516ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ns 22 data hold skew factor t qhs 0.50 0.60 0.75 0.75 1 ns active to precharge command t ras 40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns 30 active to read with auto precharge command t rap 15 15 15 20 20 ns active to active/auto refresh command period t rc 55 60 60 65 70 ns auto refresh command period t rfc 70 72 75 72 75 ns 41 active to read or write delay t rcd 15 15 15 20 20 ns precharge command period t rp 15 15 15 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck 36 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 36 active bank a to active bank b command t rrd 10 12 15 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 00000ns17, 19
w3eg7266s-ad4 -bd4 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions (continued) ddr400: v cc = v ccq = +2.6v 0.1v ac characteristics 403 355 262 265 202 parameter symbol min max min max min max min max min max units notes dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 15 15 ns internal write to read command delay t wtr 21111t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq tqh - tdqsq tqh - tdqsq ns 22 refresh to refresh command interval t refc 70.3 70.3 70.3 70.3 70.3 s 21 average periodic refresh interval t refi 7.8 7.8 7.8 7.8 7.8 s 21 terminating voltage delay to v cc t vtd 00000ns exit self refresh to non-read command t xsnr 75 75 75 75 80 ns exit self refresh to read command t xsrd 200 200 200 200 200 t ck
w3eg7266s-ad4 -bd4 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: output o u t p u t (v ( v out o u t ) reference r e f e r e n c e point p o i n t 50? 5 0 ? v tt t t 30pf 3 0 p f 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the mini-mum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are as de? ned in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ccq/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ccq/2 , v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. speci? ed values are obtained with mini-mum cycle time at cl = 2 for 262 and 202, cl = 2.5 for 265, 335 and cl = 3 for 403 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd speci? cations are tested after the device is properly initialized, and is averaged at the de? ned cycle rate. 11. this parameter is sampled. v cc = +2.5v 0.2v, v ccq = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v ccq/2 , v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, re? ecting the fact that they are matched in loading. 12. for slew rates < 1 v/ns and to 0.5 vns. if the slew rate is < 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from 500 mv/ns, while t ih is unaffected. if the slew rate exceeds 4.5 v/ns, functionality is uncertain. for 335, slew rates must be 0.5 v/ns. 13. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke < 0.3 x v ccq is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as data valid transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the dont care state after completion of the postamble is the dqs- driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high [above v ihdc (min)] then it must not transition low (below v ihdc ) prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 20. min (t rc or t rfc ) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras . 21. the refresh period 64ms. this equates to an average refresh rate of 7.8125s. however, an auto refresh command must be as-serted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the data valid window is derived by achieving other speci? cations: t hp (t ck/2 ), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec speci? es ck and ck# input slew rate must be 1v/ns (2v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncertain. for 403, slew rates must be 0.5 v/ns. 28. v cc must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 32. any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9v maximum, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2v mini-mum, whichever is more positive.
w3eg7266s-ad4 -bd4 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary 33. the voltage levels used are derived from a mini-mum v cc level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide signi? cantly different voltage values. 34. v ih overshoot: v ih (max) = v ccq + 1.5v for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. v cc and v ccq must track each other. 36. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 37. t rpst end point and t rpre begin point are not referenced to a speci? c voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). 38. during initialization, v ccq , v tt , and v ref must be equal to or less than v cc + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v cc /v ccq are 0v, provided a minimum of 42 0 of series resistance is used between the v tt supply and the input pin. 39. the current part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not re? ect this option. 40. random addressing changing and 50 percent of data changing at every transfer. 41. random addressing changing and 100 percent of data changing at every transfer. 42. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 43. i dd2n speci? es the dq, dqs, and dm to be driven to a valid high or low logic level. i dd2q is similar to i dd2f except i dd2q speci? es the address and control inputs to remain stable. although i dd2f , i dd2n , and i dd2q are similar, i dd2f is worst case. 44. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles (before read commands). 45. leakage number re? ects the worst case leakage possible through the module pin, not what each memory device contributes. 46. when an input signal is high or low, it is de? ned as a steady state logic high or low. 47. the 403 speed grade will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency.
w3eg7266s-ad4 -bd4 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary * all dimensions are in millimeters and (inches) package dimensions for bd4 67.56 (2.666) max 1.0 0.1 (0.039 0.004) 3.81 (0.150) max. 2.31 (0.091) ref. 4.19 (0.165) 1.80 (0.071) 3.98 (0.157) min. 47.40 (1.866) 11.40 (0.449) 31.75 (1.25) 3.98 0.1 (0.157 0.004) 20 (0.787) ordering information for bd4 part number speed height* commercial operating range w3eg7266s403bd4 200mhz/400mbps, cl=3 31.75 (1.25") 0c to 70c w3eg7266s335bd4 166mhz/333mbps, cl=2.5 31.75 (1.25") 0c to 70c w3eg7266s262bd4 133mhz/266mbps, cl=2 31.75 (1.25") 0c to 70c w3eg7266s265bd4 133mhz/266mbps, cl=2.5 31.75 (1.25") 0c to 70c w3eg7266s202bd4 100mhz/200mbps, cl=2 31.75 (1.25") 0c to 70c industrial part number speed height* industrial operating range w3eg7266s403bd4i 200mhz/400mbps, cl=3 31.75 (1.25") -40c to 85c w3eg7266s335bd4i 166mhz/333mbps, cl=2.5 31.75 (1.25") -40c to 85c w3eg7266s262bd4i 133mhz/266mbps, cl=2 31.75 (1.25") -40c to 85c w3eg7266s265bd4i 133mhz/266mbps, cl=2.5 31.75 (1.25") -40c to 85c w3eg7266s202bd4i 100mhz/200mbps, cl=2 31.75 (1.25") -40c to 85c notes: ? consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) ? product speci? c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a speci? c component vendor is preferred. ? consult factory for availability of industrial temperature (-40c to 85c) option
w3eg7266s-ad4 -bd4 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary 1.0 0.1 (0.039 0.004) 35.05 (1.38) max. 3.81 (0 .150) max. 2.31 (0.091) ref. 2.0 (0.079) 67.56 (2.66) max. 4.19 (0.165) 1.80 (0.071) 3.98 (0.157) min. 20 (0.787) 47.40 (1.866) 11.40 (0.449) p1 3.98 0.1 (0.157 0.004) package dimensions for ad4 * all dimensions are in millimeters and (inches) ordering information for ad4 part number speed height* commercial operating range w3eg7266s403ad4 200mhz/400mbps, cl=3 35.05 (1.38") max 0c to 70c w3eg7266s335ad4 166mhz/333mbps, cl=2.5 35.05 (1.38") max 0c to 70c w3eg7266s262ad4 133mhz/266mbps, cl=2 35.05 (1.38") max 0c to 70c w3eg7266s265ad4 133mhz/266mbps, cl=2.5 35.05 (1.38") max 0c to 70c W3EG7266S202AD4 100mhz/200mbps, cl=2 35.05 (1.38") max 0c to 70c industrial part number speed height* industrial operating range w3eg7266s403ad4i 200mhz/400mbps, cl=3 35.05 (1.38") max -40c to 85c w3eg7266s335ad4i 166mhz/333mbps, cl=2.5 35.05 (1.38") max -40c to 85c w3eg7266s262ad4i 133mhz/266mbps, cl=2 35.05 (1.38") max -40c to 85c w3eg7266s265ad4i 133mhz/266mbps, cl=2.5 35.05 (1.38") max -40c to 85c W3EG7266S202AD4i 100mhz/200mbps, cl=2 35.05 (1.38") max -40c to 85c notes: ? consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) ? product speci? c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a speci? c component vendor is preferred. ? consult factory for availability of industrial temperature (-40c to 85c) option
w3eg7266s-ad4 -bd4 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 7 preliminary document title 512mb C 64mx72, ddr, sdram unbuffered ecc, w/pll revision history rev # history release date status rev 0 initial release 1-31-02 advanced rev 1 1.1 page 1 add pll 1.2 page 5 add new table 10-10-02 advanced rev 2 1.1 add 333mhz 3-5-03 advanced rev 3 1.1 added bd4 package option/correction 2-27-04 preliminary rev 4 1.1 bd4 module dimensions corrected 1.2 ad4 module dimensions corrected 1.3 removed ed from part number 5-04 preliminary rev 5 1.0 added industrial temp spec 7-04 preliminary rev 6 1.0 added 400mhz 9-04 preliminary rev 7 1.0 added 400 mhz i dd specs 10-4 preliminary

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